Production Test Map
99 automated gates stand between make generate and a JLCPCB order.
This page is the picture of them: what each one prevents, how the EMC surface
is covered, and how the network grew release by release.
Source of truth
The roster below is VERIFY_ALL_SCRIPTS in the Makefile (95 gates) plus the
4 EMC gates being registered now. Severity is not editorial — it is what
scripts/issue_dispatch.py assigns each gate through its routing law.
A. Production test coverage map
Severity ranking
blind-spot
the gate network itself is broken, so no other verdict is trustworthy
the gate network itself is broken, so no other verdict is trustworthy
dead-board
the board does not work, or is assembled wrong
the board does not work, or is assembled wrong
degraded
it works, but out of spec — margin, heat, EMC
it works, but out of spec — margin, heat, EMC
cosmetic
documentation and rendering only
documentation and rendering only
Pipeline
Stage colour = the severity most of its gates carry. Individual gates vary — the roster below is per-gate.
The 99 gates
Source sync
11 gatesDoes the copper still match the drawing?test_enclosure_syncverify_enclosure_syncverify_firmware_retrogo_syncverify_netlist_diffverify_netlist_vs_kicadverify_schematic_crossingsverify_schematic_label_attachverify_schematic_overlapsverify_schematic_pcbverify_schematic_pcb_syncverify_schematic_pin_connectivity
Copper integrity
14 gatesIs every net one piece of copper, and nothing else touching it?short_circuit_analysistest_collision_pad_netstest_collision_via_metrictest_pcb_connectivitytest_power_net_integrityverify_component_connectivityverify_dangling_copperverify_isolationverify_net_connectivityverify_power_net_integrityverify_trace_crossingsverify_trace_through_padverify_zone_connectivityverify_zone_fill_sanity
Fabrication
14 gatesWill the fab build it as drawn, without silently correcting it?analyze_pad_distancesdrc_checkvalidate_jlcpcbverify_copper_balanceverify_copper_clearanceverify_dfm_v2verify_drill_standardsverify_gerber_integrityverify_jlcpcb_capabilitiesverify_jlcpcb_via_rulesverify_net_class_widthsverify_stackupverify_thermal_reliefverify_via_in_pad
Assembly
13 gatesWill the pick-and-place put the right part down the right way round?test_cpl_rotation_lawtest_test_pointsverify_bom_cpl_pcbverify_bom_valuesverify_cpl_rotation_lawverify_datasheetverify_datasheet_netsverify_dfaverify_easyeda_footprintverify_polarityverify_rpp_polarityverify_stencil_apertureverify_test_points
Electrical
22 gatesOnce powered, does the circuit do what it was specified to do?erc_checksimulate_circuitspice_power_checktest_erc_severitytest_esd_protectiontest_power_via_ampacitytest_strapping_en_rcverify_battery_protectionverify_decoupling_adequacyverify_decoupling_pathsverify_design_intentverify_ercverify_esd_protectionverify_ground_loopsverify_power_pathsverify_power_resonanceverify_power_sequenceverify_power_via_ampacityverify_sd_interfaceverify_signal_chain_completeverify_strapping_pinsverify_thermal_budget
Signal integrity / EMC
8 gatesDoes it still work at speed, and stay quiet while doing it?verify_antenna_keepoutverify_crosstalk *verify_length_match *verify_reference_plane *verify_usb_impedanceverify_usb_impedance_stackupverify_usb_return_pathverify_via_discontinuity *
Release integrity
11 gatesIs the thing being ordered the thing that was verified?test_claims_ledgertest_gerber_etesttest_order_manifesttest_verify_memoryverify_bringup_freshverify_claims_ledgerverify_context_budgetverify_gerber_etestverify_memoryverify_net_explorer_freshverify_order_manifest
Meta / blind-spot
6 gatesCan the gate network still be trusted to notice?test_gate_coveragetest_issue_dispatchtest_vbenchtest_vbench_displaytest_vbench_dynamicstest_vbench_sdcard
* = new EMC gate. Hover a chip for its severity.
B. EMC coverage grid
The 16 classic EMC layout mistakes, and which gate catches each one.
01PARTIAL
Broken Return Path
verify_usb_return_path
advisory outside USB
02PARTIAL
Long Loop Area
verify_dfm_v2 · verify_decoupling_paths
buck hot-loop + cap ratio
03COVERED
Split Reference Plane
verify_stackup · verify_power_net_integrity
one piece of copper per plane
04COVERED
Decoupling Placement
verify_decoupling_paths · verify_decoupling_adequacy
path length and capacitance
05NEW GATE
Signal Crossing Gaps
verify_reference_plane
traces over plane voids
06PARTIAL
Poor Ground Return
verify_ground_loops · verify_zone_connectivity
loops found, area not scored
07COVERED
Trace Spacing
verify_copper_clearance
polygon-accurate gaps
08PARTIAL
RF Shielding
verify_antenna_keepout
no shield can on board by design
09PARTIAL
Return Via Placement
verify_usb_return_path
USB pair only
10PARTIAL
High-Speed Routing
verify_usb_impedance
limits derived from bit rate
11NEW GATE
Crosstalk 3W
verify_crosstalk
parallel-run coupling
12COVERED
Uncontrolled Impedance
verify_usb_impedance_stackup
JLC04161H-7628 stackup
13NEW GATE
Trace Length Mismatch
verify_length_match
skew against edge rate
14NEW GATE
Via Discontinuity
verify_via_discontinuity
stub and count heuristics
15PARTIAL
Termination
verify_usb_impedance
USB series R proven in-path
16PARTIAL
Shield Stitching
verify_zone_connectivity
no lambda/20 spacing rule
4 covered · 4 new gates · 8 partial. "Partial" means a gate fires on the failure mode but over a narrower scope than the general rule — usually the USB pair rather than every net.
C. Version improvements
Where to go next
- Pre-Production Verification — what each gate actually asserts, and the JLCPCB threshold tables behind them
- PCBA Manufacturing & Ordering — the order package itself
make open-issues— which of these 99 gates is red right nowmake dispatch— turn every red gate into an owned work order