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Electrical Schematics

Complete electrical design for the ESP32 Emu Turbo, split into 7 detailed schematic sheets with cross-sheet global labels.

Download all sheets (PDF, 7 pages)
Source files

KiCad 10 project: hardware/kicad/

make generate-schematic   # Generate 7 .kicad_sch files
make render-schematics # Export SVG + PDF

System Block Diagram

                         ┌──────────────────┐
│ │
USB-C ──────────────>│ IP5306 Module │──── 5V rail
│ (charge+boost) │
└────────┬─────────┘

┌───────┴───────┐
│ │
┌─────┴─────┐ ┌─────┴──────┐
│ LiPo Batt │ │ AMS1117 │
│ 3.7V │ │ 5V -> 3.3V │
│ 5000 mAh │ └─────┬──────┘
│ (105080) │ │
└───────────┘ │ 3.3V

┌───────────┴───────────┐
│ ESP32-S3-WROOM-1 │
│ N16R8 (240MHz ×2) │
└──┬──┬──┬──┬──┬──┬──┬──┘
│ │ │ │ │ │ │
┌────────────┘ │ │ │ │ │ └──────────┐
│ │ │ │ │ │ │
┌─────┴─────┐ ┌─────┴──┘ │ └──┴─────┐ ┌────┴────┐
│ Display │ │ SD Card│ │ │ SPI │ │ Controls│
│ ILI9488 │ │ SPI │ │ │(coproc)│ │ 12 btns │
│ 8080 ‖ │ └────────┘ │ └───┬────┘ └─────────┘
└───────────┘ │ │
┌─────┴──┐ ┌┴─────────────┐
│USB Data│ │ESP32-S3-MINI │
│(D-/D+) │ │ -1 (v2) │
└────────┘ │ I2S → Audio │
└──────────────┘

Sheet 1 — Power Supply

USB-C input with CC pull-downs, IP5306 charge-and-play module, AMS1117-3.3 voltage regulator.

Power Supply Schematic

PDF
RefComponentValuePurposeDatasheet
J1USB-C connector5V power inputPDF
J3JST PH 2-pin connectorLiPo battery connectorPDF
R1, R2Resistor5.1 kΩCC1/CC2 pull-down (UFP identification)PDF
R16Resistor100 kΩIP5306 KEY pin pull-downPDF
R17Resistor1 kΩLED1 current limitingPDF
R18Resistor1 kΩLED2 current limitingPDF
U2IP5306 moduleLiPo charger + 5V boost (charge-and-play)PDF
BT1BatteryLiPo 3.7V 5000mAh105080 cell
U3LDO regulatorAMS1117-3.35V to 3.3V, 800mA maxPDF
L1Inductor1 µH 4.5AIP5306 boost inductorPDF
LED1Red LED0805Charging indicator (IP5306)PDF
LED2Green LED0805Fully charged indicator (IP5306)PDF
SW_PWRSlide switchSS-12D00G3Power on/offPDF
C1Capacitor10 µFLDO input decouplingPDF
C2Capacitor22 µFLDO output stabilityPDF
C17, C18Capacitor10 µFIP5306/rail decouplingPDF
C19Capacitor22 µFBulk capacitorPDF

Power Budget

ConsumerTypicalPeak
ESP32-S3 (dual-core active)150 mA350 mA
ILI9488 display + backlight80 mA120 mA
PAM8403 + speaker20 mA100 mA
SD card (SPI read)30 mA100 mA
Misc (pull-ups, buttons)10 mA20 mA
Total~290 mA~690 mA

Battery life: 5000 mAh / 290 mA ≈ 17 hours typical gameplay


Sheet 2 — MCU (ESP32-S3)

ESP32-S3-WROOM-1 N16R8 with all 35 GPIO connections grouped by function, decoupling capacitors, and EN reset circuit.

MCU Schematic

PDF
RefComponentValuePurposeDatasheet
U1MCU moduleESP32-S3-WROOM-1 N16R816MB Flash, 8MB PSRAMPDF
R3Resistor10 kΩEN pull-up (keep-alive)PDF
C3Capacitor100 nFEN reset delay (RC = 1ms)PDF
C4Capacitor100 nF3V3 decouplingPDF
SW_RSTTact switchEN reset (pulls EN low)PDF
SW_BOOTTact switchBoot mode (pulls GPIO0 low)PDF

GPIO Assignment

FunctionGPIOsSignalsBus
Display4–11D0–D78080 data
12, 13, 14, 46, 3, 45CS, RST, DC, WR, RD, BL8080 control
Audio15, 16, 17BCLK, LRCK, DOUTI2S
SD Card36, 37, 38, 39MOSI, MISO, CLK, CSSPI
D-pad40, 41, 42, 1UP, DOWN, LEFT, RIGHTGPIO
Face2, 48, 47, 21A, B, X, YGPIO
System18, 0START, SELECTGPIO
Shoulder35, 43L, RGPIO
USB Data19, 20USB_D-, USB_D+USB
Reserved GPIOs

GPIO26–32 are used internally by the PSRAM. GPIO19/20 are the native USB D-/D+ pins (firmware flash + debug console via USB CDC).


Sheet 3 — Display

ILI9488 4.0" 320×480 bare panel with 40-pin FPC, 8-bit 8080 parallel interface — mandatory for SNES emulation speed. FPC pin mapping per ILI9488 panel datasheet: pins 9-12=CS/DC/WR/RD, pin 15=RESET, pins 17-24=DB0-DB7, pin 33=LED-A(backlight), pins 6-7=VDDI/VDDA(+3V3), pins 38-39=IM0/IM1(+3V3), pin 40=IM2(GND). Note: on the PCB, display Pin N maps to connector Pad (41−N) due to the landscape FPC pass-through (see PCB docs).

RefComponentValuePurposeDatasheet
J4FPC connector40-pin 0.5mm bottom contactDisplay ribbon cablePDF

Display Schematic

PDF

The 8080 parallel mode writes a full pixel (16-bit RGB565) in 2 bus cycles. SPI would need 16 clock cycles per pixel, making it too slow for 60fps full-screen SNES rendering. GPIO4–11 form a contiguous 8-bit data bus for efficient register-level DMA.


Sheet 4 — Audio

I2S output from ESP32-S3 to PAM8403 Class-D amplifier driving a 28mm 8Ω speaker.

Audio Schematic

PDF
RefComponentValuePurposeDatasheet
U5AmplifierPAM8403Filterless Class-D, 3W/chPDF
C21Capacitor100 nF (C49678)VREF bypass capacitorPDF
C22Capacitor0.47 µF (C1525)DC-blocking cap on audio input
C23, C24, C25Capacitor1 µF (C15849)VDD and PVDD decoupling caps
R20, R21Resistor20 kΩ (C4184)Bias resistors on INL/INR to GND
LS1Speaker28mm 8Ω 0.5WMono output
note

The PAM8403 is powered from the +5V rail for maximum headroom. Only one channel is used for mono audio. ESP32-S3 I2S with DMA provides low-CPU-overhead audio streaming. The passive components (C21–C25, R20–R21) follow the PAM8403 datasheet application circuit for proper biasing, DC blocking, and power supply decoupling.


Sheet 5 — SD Card

Micro SD card module via SPI bus for ROM storage (SNES ROMs up to 6MB, FAT32).

SD Card Schematic

PDF
RefComponentDatasheet
U6Micro SD slot (TF-01A)PDF
SignalGPIODirection
MOSIGPIO36ESP32 → SD
MISOGPIO37SD → ESP32
CLKGPIO38ESP32 → SD
CSGPIO39ESP32 → SD

SPI bus up to 40MHz. GPIO36–39 are grouped for clean routing. The SD module has a built-in level shifter (3.3V safe). On the PCB, the SD card slot VCC and GND pins are connected via vias to the inner power planes (+3V3 and GND) for clean power delivery with minimal trace length.


Sheet 6 — Controls

13 tact switches (SNES layout + MENU) with individual 10kΩ pull-up + 100nF debounce per button. Plus SW_RST (reset) and SW_BOOT (boot mode) on Sheet 2. Tact switch datasheet: PDF.

Controls Schematic

PDF

Button Circuit (repeated 13×)

+3V3 ──[10kΩ R]──┬──── GPIO_x (global label)

[100nF C]

GND

[SW tact]──┤
└── GND

Idle = HIGH (3.3V via pull-up), Pressed = LOW (grounded through switch).

RefComponentValuePurpose
R4–R15, R19Resistor10 kΩ (C17414)Button pull-ups (12 + MENU)
C5–C16, C20Capacitor100 nF (C49678)Button debounce (12 + MENU)
GroupButtonsSwitchesGPIOs
D-padUP, DOWN, LEFT, RIGHTSW1–SW440, 41, 42, 1
FaceA, B, X, YSW5–SW82, 48, 47, 21
SystemSTART, SELECT, MENUSW9, SW10, SW1318, 0, —
ShoulderL, RSW11, SW1235, 43

Sheet 7 — USB Data

Native USB data lines for firmware flashing and debug console (replaces UART debug).

SignalGPIOFunction
USB_D-GPIO19USB data minus (native USB)
USB_D+GPIO20USB data plus (native USB)

USB-C now carries both power (charging via IP5306) and data (firmware flash + CDC debug console). This replaces the previous UART debug approach (GPIO43 TX0) with native USB, which is faster and requires no external UART adapter.

Joystick removed

The optional PSP joystick (previously GPIO20/GPIO44) has been removed. The D-pad provides full SNES/NES control. GPIO43 (previously TX0 for UART debug) is now used for BTN_R.


v2 — Sheet 8: Audio Coprocessor (ESP32-S3-MINI-1)

v2 addition

This sheet is only present on the v2 PCB. The v1 PCB uses direct I2S from the main ESP32-S3 to the PAM8403 (Sheet 4). In v2, the main ESP32-S3 communicates with the coprocessor via SPI, and the coprocessor drives I2S to the PAM8403.

ESP32-S3-MINI-1-N8 audio coprocessor with SPI slave interface to the main ESP32-S3 and I2S output to the PAM8403 amplifier.

RefComponentValuePurpose
U7ESP32-S3-MINI-1-N8ModuleAudio coprocessor (SPC700 + I2S)
C26Capacitor100 nF3V3 decoupling
C27Capacitor100 nFEN decoupling

SPI Bus (Main ESP32-S3 → Coprocessor)

SignalMain ESP32-S3 GPIOMINI-1 GPIODirection
SPI_CLKGPIO 15 (was I2S_BCLK)GPIO 12Main → MINI-1
SPI_MOSIGPIO 16 (was I2S_LRCLK)GPIO 11Main → MINI-1
SPI_MISOGPIO 17 (was I2S_DOUT)GPIO 13MINI-1 → Main
SPI_CSGPIO 20 (was USB_D+)GPIO 10Main → MINI-1

I2S Bus (Coprocessor → PAM8403)

SignalMINI-1 GPIODirection
I2S_BCLKGPIO 15MINI-1 → PAM8403
I2S_LRCLKGPIO 16MINI-1 → PAM8403
I2S_DOUTGPIO 17MINI-1 → PAM8403

v2 GPIO Changes vs v1

Main ESP32-S3 GPIOv1 Functionv2 FunctionNotes
GPIO 15I2S_BCLK → PAM8403SPI_CLK → MINI-1Audio path moves to coprocessor
GPIO 16I2S_LRCLK → PAM8403SPI_MOSI → MINI-1Audio path moves to coprocessor
GPIO 17I2S_DOUT → PAM8403SPI_MISO ← MINI-1Audio path moves to coprocessor
GPIO 20USB_D+ (native USB)SPI_CS → MINI-1USB D+ reassigned for coprocessor
Clean GPIO reuse

The 3 I2S pins freed by moving audio to the coprocessor are reused for SPI communication — no GPIOs wasted. GPIO 20 (USB_D+ in v1) is reassigned to SPI chip select; in v2, USB native data is no longer available (debug via SPI or UART instead).